 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TMPN3120FE5M TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TMPN3120FE5M Neuron (R) Chip For Distributed Intelligent Control Networks (LONWORKS(R)) The Neuron Chip TMPN3120FE5M provides double the performance of previous Neuron Chips. It supports a response time of 3 to 4 ms across a LONWORKS Network and has double the input / output ( I / O ) performance of the previous Neuron Chip in terms of both response time and data transmission speed. The TMPN3120FE5M features an extra single-chip memory in the form of 3 Kbytes EEPROM, 4 Kbytes SRAM and 16 Kbytes ROM. It is therefore suitable for applications which require more complex operations and high speed communication control. Neuron Chips have all the built-in communications and control functions required to implement LONWORKS nodes. These nodes may then be easily integrated into highly-reliable distributed intelligent control networks. The typical functions for this chip are explained below. FEATURES New features ( In comparison with TMPN3120E1M and TMPN3120FE5M ) * High-impedance communication port * 3 Kbytes EEPROM * 4 Kbytes static RAM Weight: 1.1g (Typ.) 000707EBA1 * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice. 2001-02-21 1/11 TMPN3120FE5M Main features of the 20 MHz Neuron Chip ( In comparison with the TMPN3120E1M and TMPN3120FE5M ) * Increased communication speed The maximum transmission speed has been increased two-fold. 1.25 Mbps 2.5 Mbps (*1) *1: This value applies to Single-Ended Mode only. * Shortened response time The amount of time required from I / O input to I / O output has been greatly reduced. Maximum speed 7 ms 3 ~ 4 ms * Increased IO object speed The execution time for all objects has been halved. Example ) Serial I / O 9600 bps Parallel I / O 1.2 s / byte * Development tool support The current LonBuilder(R) and NodeBuilder(R) development tools can be used to develop applications for the TMPN3120FE5M (L.B ver 3.01 is needed.). Updated symbol table files for the Neuron Chip firmware are available from Echelon. If your application requires a 20 MHz input clock, a utility program available from Echelon may be used to convert the programmer files * The conversion utilities can be obtained from the Echelon Web Site at http://www.echelon.com. I / O Functions * Eleven programmable I / O pins. * Two programmable 16-bit timers and counters built in. * 34 different types of I / O functions to handle a wide range of input and output. * ROM firmware image containing pre-programmed I / O drivers, greatly simplifying application programs. Network functions * Two CPUs for communication protocol processing built in. The communications and application CPUs execute in parallel. * Equipped with a built-in LonTalk protocol which supports all seven levels of the OSI reference model with ISO. * The ROM firmware image contains a complete network operating system, greatly simplifying application programs. * Built-in twisted-pair wire transceiver with improved common mode and drive current capabilities. * Equipped with communications modes and communication speeds which support various types of external transceivers. Supports twisted-pair wire, power line, radio ( RF ), infrared, coaxial cables, and fiber optics. * Communication port transceiver modes and logical addresses stored within the EEPROM. Can be amended via the network. 2001-02-21 2/11 TMPN3120FE5M Other functions * Application programs are also stored within the EEPROM. Can be updated by downloading over the network. * Built-in watch-dog timer. * Each chip has a unique ID number. Effective during the logical installation of networks. * Low electrical consumption mode supported with a sleep mode. * Built in Selectable Reset time Prolongs the power-ON reset time for at least 50 ms and keeps the operation stable during that time. The reset time can be selected 50ms delay mode or 3 clock delay mode by program after the device is in power-ON. * High-impedance communication port ( CP0 to CP3 ) The Communication port pins ( CP0 to CP3 ) attain high impedance. This eliminates the need for an external relay. * Built-in low-voltage detection circuit. Prevents incorrect operations and writing errors in the EEPROM during drops in power voltage. An external LVD must be used to assert reset at power supply voltage below 4.5 V if Neuron Chip is operated at 20 MHz. * Programmable LVD (Low Voltage Detection) circuit. LVDin pin is prepared in order to make it reset on arbitrary voltage. * Firmware version 10. Timing for the main I / O objects during 20 MHz Neuron Chip operations I / O MODEL Parallel Bitshift Magcard Magtrack1 Neurowire Master Neurowire Slave Serial Touch Frequency Output 10 MHz TIMING 2.4s / byte 1, 10 or 15 kbps Up to 8334 bps Up to 7246 bps 1, 10 or 20 kbps Up to 18 kbps 600, 1200, 2400 or 4800 bps Supported Resolution0.4 to 51.2s Max Range 26.21 to 3355 ms Resolution0.2 to 25.6s Max Range 13.1 to 1678 ms 20 MHz TIMING 1.2s / byte 2, 20 or 30 kbps Up to 16668 bps Up to 14492 bps 2, 20 or 40 kbps Up to 36 kbps 1200, 2400, 4800 or 9600 bps Not supported Resolution0.2 to 25.6s Max Range 13.1 to 1678 ms Resolution0.1 to 12.8s Max Range 6.55 to 839 ms Other Timer / Counter The specifications for the main timers during 20 MHz operations are as follows : Watchdog Timer Millisecond Timers Second Timers Delay ( ) Function Get_Tick_Count ( ) Function 420 ms 1 to 32000 ms 1 to 65000 s 1 to 32767 counts 409.6s per count 2001-02-21 3/11 TMPN3120FE5M BLOCK DIAGRAM ITEM CPU RAM ROM EEPROM 16-bit Timer / Counter External Memory Interface Package TMPN3120FE5M 8-bit CPU x 3 4,096 bytes 16,384 bytes 3,072 bytes 2 channels Not available 32-pin SOP 2001-02-21 4/11 TMPN3120FE5M PIN CONNECTION 2001-02-21 5/11 TMPN3120FE5M PIN FUNCTION PIN No. 15 14 1 PIN NAME CLK1 CLK2 ~RESET I/O Input Output I/O (built-in pull-up) I/O 8 ~SERVICE (built-in configurable pull-up) I/O I/O 3, 30~28 IO4~IO7 (built-in configurable pull-up) I/O Input Input Input I/O Service pin. Indicator output during operation. PIN FUNCTION Oscillator connection, or external clock input. Oscillator connection. Leave open when external input to CLK1. Reset pin. ( Active low ) clock is 7~4 IO0~IO3 Large current sink capacity ( 20 mA ). General I / O port. General I / O port. One of IO4 to IO7 can be specified as No.1 timer / counter input. Output signal can be output to IO0. IO4 can be used as the No.2 timer / counter input with IO1 as output. General I / O port. Can be used for serial communication with other device. Power input ( 5.0 V Typ. ) Power input ( 0 V GND ) Input pin for programmable LVD ( Normally connect to VDD ) Bidirectional port for communications. Supports several communications protocols by specifying mode. 27, 26, 24 11, 12, 18, 25, 32 9, 10, 13, 16, 23, 31 2 19, 20, 17, 21, 22 IO8~IO10 VDD VSS LVDin CP0~CP4 *: The ~SERVICE and IO4 to IO7 terminals are programmable pull-ups. All VDD terminals must be externally connected. All VSS terminals must be externally connected. 2001-02-21 6/11 TMPN3120FE5M MAXIMUM RATINGS ( VSS = 0V, VSS typ.) ITEM Power Supply Voltage Input Voltage Input Voltage CP0-CP3 Drain Current Source Current Power Dissipation Storage Temperature SYMBOL VDD VIN (1) VIN (2) IDD ISS PD Tstg RATING -0.3~7.0 -0.3 to VDD + 0.3 V -0.5 to VDD + 1.3 V VIN (2) 7.3 (Note 1) 200 300 800 -65~150 UNIT V V V mA mA mW C Note1 : VIN(2) don't exceed the 7.3v. OPERATING CONDITIONS ITEM Operating Voltage Input Voltage ( TTL ) SYMBOL VDD VIH VIL VIH VIL VIH VIL fosc Topr MIN 4.5 2.0 VSS VDD - 0.8 V VSS -0.1 0.625 -40 TYP. 5.0 MAX 5.5 VDD 0.8 VDD 0.8 VDD + 1.0 V 20 85 UNIT V V V V V V MHz C Input Voltage ( CMOS ) Input Voltage CP0-CP3 ( differential mode ) Operating Frequency Operating Temperature 2001-02-21 7/11 TMPN3120FE5M ELECTRICAL CHARACTERISTICS DC characteristic ( VDD = 5.0 V 10%, VSS = 0 V, Ta = -40~85C ) ( Above operating conditions apply unless otherwise states. ) ITEM SYMBOL PINS IO0~IO10 CP0, CP3, CP4, ~SERVICE ~RESET IO0~IO10 CP0, CP3, CP4, ~SERVICE ~RESET IO0~IO3 ~SERVICE, ~RESET CP2, CP3 Others ( Note 1 ) IO0~IO3 ~SERVICE CP2, CP3 Others ( Note 1 ) ( Note 2 ) IO4~IO7 ~SERVICE, ~RESET VDD TEST CONDITION MIN MAX UNIT LOW Level Input Voltage (1) VIL (1) VIL (2) VIH (1) VIH (2) VOL (1) VOL (2) VOL (3) VOH (1) VOH (2) VOH (3) VOH (4) IIN IPU (Note 3) VLVD 0 0.8 VDD x 0.3 VDD VDD 0.8 0.4 1.0 0.4 VDD VDD VDD VDD 10 -300 4.5 V LOW Level Input Voltage (2) 0 V HIGH Level Input Voltage (1) 2.0 VDD - 0.7 V 0 0 0 0 VDD - 0.4 V VDD - 0.4 V VDD - 1.0 V VDD - 0.4 V -10 -30 V HIGH Level Input Voltage (2) IOL = 20mA IOL = 10mA IOL = 40mA IOL = 1.4mA IOH = -1.4mA IOH = -1.4mA IOH = -40mA IOH = -1.4mA VIN = VSS~VDD VIN = 0V V LOW Output Voltage (1) LOW Output Voltage (2) LOW Output Voltage (3) HIGH Output Voltage (1) HIGH Output Voltage (2) HIGH Output Voltage (3) HIGH Output Voltage (4) Input Current Pull-up Current Low-voltage Detection Level V V V V V V V A A V 3.8 Note1 : Output voltage characteristics exclude the CLK2 pin. Note2 : Excludes pull-up input pins. Note3 : The IO4 to IO7 and ~SERVICE pins have programmable pull-ups. ~RESET has a fixed pull-up. 2001-02-21 8/11 TMPN3120FE5M ITEM 20 MHz Clock 10 MHz Clock Operating Mode Current Consumption 5 MHz Clock 2.5 MHz Clock 1.25 MHz Clock 0.625 MHz Clock Sleep Mode Current Consumption IDD (SLP) IDD (OP) SYMBOL TYP. 34 16 8.5 4.5 2.3 1.3 16 MAX 55 30 15 8 5 3 100 A mA UNIT Note : Test conditions for current dissipation VDD = 5V, all output = with no load, all input = 0.2 V or below or VDD - 0.2 V, programmable pull-up = off, crystal oscillator clock input, differential receiver disabled. The current value ( typ. ) is a typical value when Ta = 25C. The current value ( max ) applies to the rated temperature range at VDD = 5.5 V. 200A ( typ. ) to 600A ( max ) is added to the current of the differential receiver when the receiver is enabled. The differential receiver is enabled by either of the following conditions : When the Neuron Chip is in Run mode and the communication ports are in Differential mode. When the Neuron Chip is in Sleep mode, the communication ports are in Differential mode, and the Comm Port Wakeup is not masked. 2001-02-21 9/11 TMPN3120FE5M Echelon, Neuron, LON, LonTalk, LonBuilder, NodeBuilder, LONWORKS, 3150, 3120 and LonManager are the registered trade marks of America's Echelon Inc. The Neuron Chip is manufactured by Toshiba under license from Echelon Corporation, USA. A licensing agreement between the customer and Echelon Corporation must be concluded before purchasing any of the neuron chip products. The Neuron chip itself does not include the I2C object function. You need the "I2C Library" delivered by Echelon. The Neuron chip and the I2C Library do not convey nor imply a right under any I2C patent rights of Philips Electronics N.V. ( "Philips" ) to make, use or sell any product employing such patent rights. Please refer all questions with respect to I2C patents and licenses to Philips at: Mr. Gert-Jan Hessenlmann Corporate Intellectual Property Philips International B.V. Prof. Holstlaan 6 Building WAH 1-100 P.O. Box 220 5600 AE, Eindhoven, The Netherlands Phone : +31 40 274 32 61 Fax : +31 40 274 34 89 E-mail : Gert.Jan.Hesselmann@philips.com. 2001-02-21 10/11 TMPN3120FE5M PACKAGE DIMENSIONS 2001-02-21 11/11 |
Price & Availability of TMPN3120FE5M
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |